A system of packaging used to package Integrated Circuits (ICs), in semiconductor industries, is called Wafer Level Package (WLP). ICs are very fragile and are prone to contamination. Improper packaging of ICs can lead to its inappropriate functioning. And, since Wafer level Packaging is used to package these frail ICs it is of crucial importance. WLP finds application in the ICs which are used in portable consumer electronic devices such as smart phones. Rising demand of the consumers for technologically improved mobile devices capable of carrying out a variety of functions in a single small end product is one of the main factors propelling the market for WLP technology. Moreover, low cost of the wafer level packaging in comparison to the conventional method of packaging is expected to amplify the market for WLP technology during the forecasted period.

Currently, the global WLP market has witnessed significant growth due to the change in infrastructure of the electronics industry and the expanding demand for the portable consumer electronic devices.  High performing compact electronic devices and the cost efficient packaging in the semiconductor packaging industry are the main factors driving the WLP technology market. In addition, speedy advancements of the fabrications of integrated circuits are aiding the growth of the WPL technology market in semiconductor packaging industry. This is mainly because intrinsically wafer level packaging is chip size package and has a very small form factor. Wafer level packaging is cost effective compared to die level packaging. Therefore, an increase in the wafer size, or a decrease in the die size in the die level packaging causes the packaging cost of the ICs to become higher than the cost of manufacturing ICs. Whereas, in wafer level packaging it is possible to compare the per unit wafer cost to the total IC cost. This implies that WLP is more cost efficient for decreased die size or increased wafer size. Hence IC manufacturers are incorporating WLP in their designs.

Wafer level packaging technology also helps in minimizing the consumption of electricity, has prolonged battery life for cell phones, and has a compact structure which aids the manufacturers to develop and design ultra-thin cell phones.. Despite all these, there are certain factors which is restraining the growth of the WLP market. One such factor is the fluctuation in certain physical properties of the WLP technology, like the coefficient of thermal expansion of the materials of the wafer technology as compared to the materials of Integrated Circuits (ICs). Coefficient of thermal expansion of materials reduces the durability of WLP, thereby reducing its lifespan. This is expected to effect the consumption of WPL in an adverse manner since people prefer durable products with long life span as opposed to non-durable products with short life-span.

The main opportunity for the WPL market is the increasing trend in the usage of ultra-thin android cell phones in both developed and developing countries. Wafer level packaging is a major component for these generation of smart phones. And, an increasing demand for these cell phones necessarily implies an increase in demand for WLP in the near future.

The global Wafer Level Packaging (WLP) market can be segmented on the basis of integration, technology, application and geography. By integration, the WLP market can be sub-segmented as integrated passive device, fan in WLP, fan out WLP, and through-silicon via.By technology the global WLP market can be categorized as flip chip, compliant WLP, conventional chip scale package, wafer level chip scale package, nano wafer level packaging, and 3D wafer level packaging. On the basis of application the global wafer level technology market can be sub-divided into industrial, automotive, medical, consumer electronics, defense, and aerospace. By geography the global WLP can be categorized as North America, Asia-Pacific, Europe and the Rest of the World (RoW).

The key players in the global WPL market include STATS ChipPAC Ltd, NemotekTechnologie S.A., Chipbond Technology Corporation, Fujitsu Limited, Powertech Technology Inc., Jiangsu Changjiang Electronics Technology Co. Ltd., China Wafer Level CSP Co. Ltd., TriQuint Semiconductor Inc., Siliconware Precision Industries Co. Ltd., Amkor Technology Inc., IQE PLC, and ChipMOS Technology Inc..

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Wafer Level Packaging Market

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